Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, a delta-sigma modulator spreads the quantization noise power across an oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, the delta-sigma modulator performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; hence, most of the quantization noise power is thereby shifted out of the signal band.
The typical delta-sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, quantizer and a feedback loop with a digital to analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in a higher order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. Higher-order modulators have improved quantization noise transfer characteristics over those of lower order, but stability becomes a more critical design factor as the order increases.
Switched-capacitor filters/integrators are useful in a number of applications including the integrator stages in delta-sigma modulators. Generally, a basic differential switched-capacitor integrator samples the input signal, and often a reference voltage as well, onto a corresponding pair of sampling capacitors during the sampling (charging) phase. During the following charge transfer phase, the charge on the sampling capacitor is transferred at the summing nodes of an operational amplifier to a corresponding pair of integrator capacitors in the amplifier feedback loops. The operational amplifier drives the integrator output.
Noise performance is an important design constraint in delta-sigma modulator design. Noise can result from a number of different factors, including parasitic capacitances and timing mismatches. Settling time is another constraint on noise performance when switched-capacitor integrator stages are utilized. Generally, sufficient time must be provided during the charge transfer phases to allow the voltages at the opamp inputs to settle to their steady state values. This time requirement in turn limits the switching speed of the integrator stage, and consequently the operating speed of the overall system, or alternatively limits noise performance.
Reducing input impedance of a switched capacitor integrator stage is a further important design consideration. A higher input impedance will allow the integrator stage to be driven by a smaller, less complicated, and/or less expensive driver circuit.
Hence, for applications requiring low-noise delta-sigma modulation, improved techniques for reducing noise are required. Another goal is the reduction of the input impedance at the input sampling network, such that smaller, less complicated, external drivers may be utilized. Finally, improvement of modulator performance at high frequencies is an additional design consideration, which should be addressed.